Spatially-Multiplexed Architecture for Short-Range Wireless Communication With Increased Capacity

Web Published:

High Capacity Wireless Interconnect Architecture

Docket # 14-2991


Metal-based interconnect traces on PCB boards serve as the most common method of chip-chip interconnects.  However, the increasing need of computational power requires that the communication data-rate from the processor to the peripherals be scaled proportionately. Current methods of scaling of electrical interconnects to higher data rates are either limited by the available bandwidth density, energy cost and the circuit complexities in driving high-speed data through lossy physical traces, or form factor constraints. Optical interconnects are limited in cm-range applications due to their added complexity of non-integrable laser sources, the increased energy overhead for electrical-optical and optical-electrical conversion, and temperature sensitivity. This has created an ‘interconnect gap’ for ultra-high-speed and energy-efficient interconnect solution in the cm-range. As we are ushered into the era of `big data’ and tera-scale computing, massive amounts of data crunching by these processors or interconnected mobile devices will require inordinately large amount of bandwidth not currently served by either electrical or optical interconnect solutions.

To address these issues, researchers in the Department of Electrical Engineering at Princeton University have developed a wireless architecture integrable in silicon chipsets where multiple simultaneous parallel streams of data are upconverted into the same mm-Wave carrier frequency near 100 GHz. The high carrier frequency provides the bandwidth necessary for each data stream to support multi-10Gb/s, while the spatial multiplexing architecture enables increasing the capacity by an order of magnitude without occupying more bandwidth. The wireless communication link is flexible, not constrained by form-factor and easily reconfigurable among all the communication devices, enabling seamless communication links between the connected devices.



·         Ultra-high speed wireless connectivity at short range between

o   Processor and peripherals

o   Server backplanes

o   Mobile devices


·         Enables seamless communication between connected devices


·         Energy-efficient wireless connectivity up to multi-100 Gb/s at short distances


·         Wireless communication link is

o   Flexible

o   Reconfigurable

o   Not constrained by form-factor


Current wireless connectivity at 60 GHz has demonstrated 10 Gb/s at 60 pJ/bit energy dissipation, but falls way short of meeting the bandwidth requirements for future off-chip interconnects (multi-100 Gb/s progressing towards to 1.0 TB/s). In this application, we propose multiple parallel wireless channels that can work simultaneously sharing the same frequency and channel using communication theoretic spatial-domain multiplexing techniques. Under the same total power constraint, such architectures have orders of magnitude more channel capacity, thereby providing a scalable solution towards wireless multi-100 Gb/s connectivity.

At such high mmWave frequencies, where the wavelength in silicon is a few 100 μm, multiple such antennas and wireless transceivers acting as wireless hubs could be integrated in one chip. Each such hub establishes separate multi-10 Gb/s wireless links with each such hub of the communicating chip/device. All the channels operate simultaneously by radiating the data wirelessly from the chip with onchip antennas. Evidently, for simultaneous operation, frequency-domain-multiplexing is impractical since it requires multiple frequency synthesizers covering 100s of GHz. In this methodology, we overcome this through spatial-domain multiplexing using communication theoretic MIMO techniques in both line-of-sight and non-line-of-sight links. This enables the net capacity to progress towards multi-100 Gb/s.


Faculty Inventor

Kaushik Sengupta is an Assistant Professor in the Department of Electrical Engineering at Princeton University.  He received the B.Tech. and M.Tech. degrees in electronics and electrical communication engineering from Indian Institute of Technology (IIT), both in 2007, and the MS and PhD degrees in electrical engineering from the California Institute of Technology in 2008 and 2012, respectively. In February 2013, he joined the faculty of the Department of Electrical Engineering at Princeton University. His research interests are in the areas of integrated electronic and photonic circuits and systems, electromagnetics, optics for various applications in sensing, imaging and high-speed communication.


Dr. Sengupta received the Charles Wilts prize for the best thesis in Electrical Engineering at Caltech in 2012-13. He was the recipient of the IBM PhD fellowship (2011-12), the IEEE Solid State Circuits Society Predoctoral Achievement Award, the IEEE Microwave Theory and Techniques Graduate Fellowship, and the Analog Devices Outstanding Student Designer Award (2011). He was also the recipient of the Prime Minister Gold Medal Award of IIT (2007), the Caltech Institute Fellowship, the Most Innovative Student Project Award of the Indian National Academy of Engineering (2007), and the IEEE Microwave Theory and Techniques Undergraduate Fellowship (2006). He was the co-recipient of IEEE RFIC Symposium Best Student Paper Award in 2012.


Intellectual Property Status

Patent protection is pending.

Princeton is seeking industrial collaborators for the further development and commercialization of this opportunity.  


Michael Tyerech

Princeton University Office of Technology Licensing • (609) 258-6762•

Laurie Bagley

Princeton University Office of Technology Licensing • (609) 258-5579•



Patent Information:
For Information, Contact:
John Ritter
Princeton University
Kaushik Sengupta