A New Design of Cache Memory in Computers that Improves Performance and Security

Web Published:
10/30/2014
Description:

Princeton Docket #09-2526-1

 

The invention is a new method of designing cache memories used in computers. It achieves best-in-class performance for various performance metrics, previously achievable only by different conventional cache architectures. In particular, it combines benefits of Fully-Associative caches and Direct-Mapped caches, in a novel way different from conventional Set –Associative caches. In addition, it also provides security from cache-based side-channel attacks, which can cause information leakage, such as leaking the secret key of ciphers implemented by software running on computers. All current caches are susceptible to cache side-channel attacks.  This hardware secure cache solution is much faster than software solutions for mitigating cache side-channel attacks, which require customized modifications of each software implementation. In contrast, the secure cache can protect legacy software without modification, across different cryptographic algorithms and cache side-channel attacks. In addition, this new cache architecture provides other benefits like fault-tolerance, hot-spot mitigation and flexible partitioning for cache memories, with much lower impact on performance. The security-enabling and performance-enabling features are integrated into a new cache design for computers or any programmable devices. The new cache design is easy to implement and integrate into existing microprocessor, embedded processor, micro-chip, SOC (System On Chip) and computer designs.

Faculty Inventor

 

Ruby B. Lee is the Forrest G. Hamrick Professor in Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science Department. She is the director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Professor Lee is an expert in hardware-enhanced security and has designed architectures for secure processors, secure caches that do not leak information through side-channel attacks, and secure servers for cloud computing. Her research is in the intersection of computer architecture and cyber security. She is a Fellow of the Association for Computing Machinery (ACM) and a Fellow of the Institute of Electrical and Electronic Engineers (IEEE). She holds over 120 U.S. and international patents.

 

Intellectual Property Status

 

Patent granted:

 

US 8,549,208

https://www.google.com/patents/US8549208

US 9,110,816

https://www.google.com/patents/US9110816

 

Princeton is seeking to identify appropriate partners for the further development and commercialization of this technology.

Contact

 

Michael Tyerech
Princeton University Office of Technology Licensing

(609) 258-6762• tyerech@princeton.edu

 

Xin (Shane) Peng

Princeton University Office of Technology Licensing

(609) 258-5579• xinp@princeton.edu

 

 

Patent Information:
Category(s):
Computers and Software
For Information, Contact:
Michael Tyerech
former Princeton Sr. Licensing Associate
Princeton University
mtyerech@rd.us.loreal.com
Inventors:
Ruby Lee
Zhenghong Wang
Keywords:
computers/software
data security
microprocessor