Hardware/Software Architecture for Improving the Safety of Implantable and Wearable Medical Devices
Princeton Docket # 16-3226-1
Implantable and wearable medical devices (IWMDs) have become increasingly sophisticated over the years and are now commonly equipped with advanced features. However, unsafe operations of IWMDs such as software bugs, malicious attacks, or even user errors are of utmost concern to patients since they can be life-threatening.
Inventors at Princeton University in the Department of Electrical Engineering and at Purdue University have developed a novel approach for enhancing the IWMD's safety, identifying unsafe IWMD operations, and preempting them before they can have an adverse effect on the patient.
There are many considerations in the design of a safe IWMD architecture. For example, high-level context awareness is essential for accurate decision making regarding safety. Additionally, unsafe operations should be identified and blocked in a proactive manner before they are performed, because operations of IWMDs may be irreversible. It is preferred that the safety checking be performed in a computing environment that is isolated from the normal functions of the medical device to prevent propagation of failure. Further, due to the stringent power constraints imposed on IWMDs, the power overheads imposed by the checking mechanism should be kept be as low as possible.
• Safety monitoring and attack preemption for IWMDs
• High visibility of the operational state of IWMDs
• Control of the IWMD immediately following the detection of unsafe operations
• Isolation of safety assurance mechanism from medical functionality of IWMDs
• Can be integrated into existing IWMDs
• Low power requirement
This invention describes a hardware/software architecture for improving the safety of IWMDs. The safety coprocessor is integrated into the IWMD such that it has full visibility of the I/O transactions performed by the host microcontroller. Utilizing the transaction information, the coprocessor applies a multi-layered decision process to evaluate the safety of IWMD operations. In order to ensure that unsafe operations are pre-empted, all actuator commands issued by the host microcontroller need to be validated by the safety coprocessor before they can reach the appropriate peripherals. In effect, the safety coprocessor acts as a last line of defense to prevent unsafe operations from affecting the patient. To provide for flexible and robust safety checking, the safety coprocessor was implemented using a low-power microcontroller that is physically isolated from the host microcontroller within the IWMD.
Development to Date
A safety-enhanced IWMD controller board based on the proposed architecture has been implemented. Cortex M4 high-performance embedded microcontroller was used as the host microcontroller that executes the device firmware and the Cortex M0+ low-power microcontroller as the safety coprocessor. Multi-layered safety rule checking based on control-flow of the device firmware, I/O transactions of the host microcontroller, and the patient's inferred physiological state, was used to detect unsafe behavior.
Implantable and wearable medical devices, safety, coprocessor, host microcontroller, multi-layered decision, unsafe operations, preemption.
The Faculty inventor
Niraj K. Jha, Professor of Electrical Engineering
Professor Niraj K. Jha completed his doctoral studies in Electrical Engineering at the University of Illinois at Urbana-Champaign in 1985. He holds a M.S. in Electrical Engineering from the State University of New York at Stony Brook and a B.Tech. in Electronics and Electrical Communication Engineering from the Indian Institute of Technology. He joined Princeton University in 1987, achieving the rank of Professor in 1998.
Prof. Jha is a fellow of IEEE and the Association for Computing Machinery (ACM) and has served as the Editor-in-Chief of IEEE Transactions on VLSI Systems, and as an Associate Editor of several journals. He has been the recipient of the AT&T Foundation Award, NEC Preceptorship Award for Research Excellence, the NCR Award for Teaching Excellence, and the Princeton University Graduate Mentoring Award. He has co-authored or co-edited five books, in addition to authoring or co-authoring 15 book chapters and more than 410 technical papers. He has won nine best paper awards and six best paper award nominations. In addition, his papers have been selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years,” by IEEE Micro Magazine as top picks from the 2005 and 2007 Computer Architecture conferences, and two were included among the most influential papers of the last 10 years at the IEEE Design Automation and Test in Europe Conference. He holds 16 U.S. patents.
The research interests of the Jha lab include power- and temperature-aware chip multiprocessor (CMP) and multiprocessor system-on-chip (MPSoC) design, design algorithms and tools for FinFETs, three-dimensional integrated circuit (3D IC) design, embedded system analysis and design, field-programmable gate arrays (FPGAs), digital system testing, computer security, quantum circuit design, and energy-efficient buildings.
Intellectual Property Status
Patent applications are pending. Princeton is seeking industrial collaborators for further development and commercialization of this technology.
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