Random and Safe (RaS) Cache Architecture to Defeat Cache Timing Attacks

Web Published:
10/7/2024
Description:

Random and Safe (RaS) Cache Architecture to Defeat Cache Timing Attacks

Princeton Docket # 25-4192-1

Princeton University researchers have developed an innovative hardware solution known as Random and Safe (RaS) caches to address critical security vulnerabilities in modern computer systems. This technology significantly enhances security by effectively preventing side-channel and speculative execution attacks that exploit cache timing channels. Unlike current hardware security proposals, which often partition hardware resources, leading to scalability issues, RaS caches maintain high performance without compromising resource allocation. They generate secure memory fetches that are resistant to cache timing attacks without the need for cache partitioning. RaS also provides a more effective solution than current software-based options by eliminating the significant slowdowns in performance. Furthermore, RaS caches can be seamlessly integrated into processor designs without requiring major architectural changes.

The versatility of RaS architecture allows it to be implemented across a wide range of computing platforms, including general-purpose computers, cloud computing servers, notebook computers, military systems, financial services, and healthcare applications. Overall, this groundbreaking technology developed by Princeton University researchers has the potential to improve data security across the computing landscape, providing a powerful new defense in the ongoing battle against information leakage.

 

Applications
•    Hardware security feature
•    Intrinsically secure cache 
•    Prevent cache-based side-channel and speculative execution attacks 
•    Cybersecurity for any sector 

 

Advantages
•    Superior protection
•    Security-performance trade-offs
•    Easy integration into processor architecture
•    No hardware resource usage restrictions 

 

Stage of development
This hardware security feature has been implemented and tested in GEM5, where benchmarks and tests for security and performance were conducted and confirmed. 

 

Citations
https://arxiv.org/abs/2309.16172

 

Inventors
Ruby Lee Ph.D. is a Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University. Her research is on cybersecurity, computer architecture, and deep learning. She is known for her expertise in hardware security architectures.
Guangyuan Hu is a Ph.D. candidate in the Department of Electrical and Computer Engineering at Princeton University. His primary research areas include computer architecture, security and machine learning.

 

Intellectual Property & Development status
Patent protection is pending.
Princeton is currently seeking commercial partners for the further development and commercialization of this opportunity. 

 

Contact
Princeton University Office of Technology Licensing
Tony Williams • (609) 258-3769 • anthonyw@princeton.edu

 

Patent Information:
For Information, Contact:
Tony Williams
Associate Director
Princeton University
609-259-3769
anthonyw@Princeton.edu
Inventors:
Ruby Lee
Guangyuan Hu
Keywords: