HARDWARE TRUST ANCHORS IN SP-ENABLED PROCESSORS

Web Published:
11/30/2011
Description:

Princeton Docket #09-2495-1

 

Researchers at Princeton have developed a new device to improve the security of computers, communication devices and entertainment devices. The invention consists of a set of hardware registers and mechanisms that define a small set of fundamental hardware trust anchors, and cryptographic and tagging mechanisms that can be implemented in any processor or SOC used in computing, communications or entertainment devices. It is made by building the SP hardware features into any processor chip or SOC (system on chip) or FPGA attachment. These new SP hardware features can be used to protect trusted software, which is bound to the device. The trusted software can use the hardware trust anchors as root secrets to protect other secret or sensitive information for many different usage scenarios. For example, it can provide transient trust for sensitive information needed by first responders for emergency response, which can be reliably revoked at the end of the emergency. It also provides hardware-enforced policy-controlled secrets belonging to different organizations, and remote attestation and secure communications with a trusted entity.

 

The device is much simpler than industry's currently used Trusted Platform Module (TPM) as it does not require costly public-key cryptography, a separate chip and external trusted databases for checking integrity measurements of code. Additionally, it does not require the commodity operating system to be trusted.

 

It is anticipated that this new device can be implemented in microprocessors, embedded processors, application-specific processors, security processors, cryptoprocessors, communications processors, coprocessors and SOCs (System on Chips) to simplify architecture and improve security.

 

Faculty Inventor

 

Ruby B. Lee is the Forrest G. Hamrick Professor in Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science Department. She is the director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Professor Lee is an expert in hardware-enhanced security and has designed architectures for secure processors, secure caches that do not leak information through side-channel attacks, and secure servers for cloud computing. Her research is in the intersection of computer architecture and cyber security. She is a Fellow of the Association for Computing Machinery (ACM) and a Fellow of the Institute of Electrical and Electronic Engineers (IEEE). She holds over 120 U.S. and international patents.

 

Intellectual Property Status

 

Patent protection is pending.

 

Princeton is seeking to identify appropriate partners for the further development and commercialization of this technology.

 

Contact

 

Michael Tyerech
Princeton University Office of Technology Licensing

(609) 258-6762• tyerech@princeton.edu

 

Laurie Bagley
Princeton University Office of Technology Licensing

(609) 258-5579• lbagley@princeton.edu

Patent Information:
Category(s):
Computers and Software
For Information, Contact:
Michael Tyerech
former Princeton Sr. Licensing Associate
Princeton University
mtyerech@rd.us.loreal.com
Inventors:
Ruby Lee
Jeffrey Dwoskin
Keywords:
computers/hardware
data security
microprocessor
system on chip (SOC)