Researchers at Princeton University led by Professor Margaret Martonosi
have developed a novel technology to dramatically reduce power consumption in
commercial microprocessors. Princeton is currently seeking industrial
collaborators to commercialize this technology.
State of the art processor designs have been pushed towards 64-bit
word-widths because of the large address space needs in current applications.
Although full 64-bit addresses and operations are indeed sometimes needed,
arithmetic operations on much smaller quantities are still more common. Across
the SPECint95 benchmarks, over half the integer operation executions require 16
bits or less. Based on this date, Professor Martonosi and her group have
developed a hardware mechanism that dynamic ally recognizes these narrow-width
This optimization reduces power consumption by using operand-value-based
clock gating to turn off portions of arithmetic units that will be unused by
narrow width operations and results in a 50% reduction in the integer unit's
power consumption for the SPECint95 and MediaBench benchmark suites. It is
anticipated that additional work will lead to further power reductions within
other units of the processor.
Applications would include a wide range of commercial microprocessors
including high end systems to reduce the costs of chip packaging and heat
dissipation and to extend the battery life in notebooks and other embedded
systems. Moreover, increased demand for this type of technology is expected as
the usage of larger word-width microprocessors becomes more prevalent in
printers, routers, multimedia, etc.
Patent protection is pending.
For more information please
William H. Gowen
Office of Patents and
New South Building
Princeton, NJ 08544-0036
(609) 258-1159 fax